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SY87725L
2.5Gbps GPON/BPON ONU SERDES
General Description
The SY87725L is a single chip transceiver for data rates up to 2.5Gbps. On the receive side, it includes a complete clock recovery and data retiming circuit with an integrated 4-bit serial-to-parallel data converter. On the transmit side, it includes a synthesizer with an integrated 4-bit parallel-to-serial data converter. The SY87725L receiver has a synthesizer that generates an internal clock from an externally supplied TTL or PECL REFCLK that can be either 155.52MHz or 77.76MHz. This internal clock can be used by the clock recovery PLL if an absence of transitions on the input serial data stream prevents normal clock recovery. This enables it to provide a stable clock source in the absence of transitions on the incoming serial data stream. The transmit synthesizer uses the CLKIN parallel data clock to generate its own serial rate clock locked to CLKIN. This enables the transmit and receive to operate at different data rates. The serial interface for both the transmit and receive functions feature industry standard high-speed differential CML I/O. The parallel interfaces feature highspeed LVDS I/O with an internal 100 termination on the LVDS inputs. The first bit for the serial-to-parallel conversion can be moved using the RCV_SYNC input. The RCV_SYNC input enables the parallel word boundary to move up in time by one bit time for each pulse. This allows it to in effect "swallow" one bit each time the RCV_SYNC pulse is asserted. Datasheets and support documentation can be found on Micrel's web site at: www.micrel.com.
Features
Single 3.3V supply and 1W typ. power consumption 2.5G/1.25G/625Mbps down stream 1.25G/625M/156Mbps up stream 4-bit Serdes with LVDS interfaces Serial Data input sensitivity of 30mV typical Training mode for fast lock acquisition Link Fault Indicator (LFIN: "HIGH" = Locked) Separate training and MUX synthesizers Loop back function for diagnostics TTL-CML Translator for MAC-to-Laser diode driver burst control * Selectable double data rate option for low cost FPGA/ASIC MAC implementation * Available in Pb-Free (10mm x 10mm) 64-pin EPAD-TQFP * * * * * * * * * *
Applications
* BPON/GPON/GEPON/EPON
Markets
* FTTH/FTTP
Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
February 2007
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SY87725L
Functional Block Diagram
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SY87725L
Pin Configuration
64-Pin EPAD-TQFP (T64-1)
Ordering Information
Part Number SY87725LHY SY87725LHYTR
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25 C, DC electricals only. 2. Tape and Reel.
o
Package Type H64-1
(2)
Operating Range Industrial Industrial
Package Marking SY87725LHG with Pb-Free bar-line indicator SY87725LHG with Pb-Free bar-line indicator
Lead Finish Pb-Free Matte-Sn Pb-Free Matte-Sn
H64-1
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SY87725L
Pin Description
RECEIVE SECTION SIGNALS Pin Number 55, 56 Pin Name SINP, SINN Pin Description Serial Data In (Differential LVPECL Input): This input receives the serial differential data stream. An internal PLL recovers the embedded clock and data. Reference Clock (TTL or Differential LVPECL Input): This input accepts either singleended TTL or differential LVPECL signals and is used as the reference for the internal frequency synthesizer and the "training" frequency for the receiver PLL to keep it centered in the absence of data at the SIN input. The REFCLKN input has an internal reference circuit that applies the threshold voltage in case of a single-ended TTLsignal at REFCLKP. REFCLKN has an internal 75k to GND and can be left open
60, 61
REFCLKP, REFCLKN,
in that case.
15 6, 7 1, 2 59 3, 5 39, 40, 41, 42, 43, 44, 45, 46 33, 34 36, 37 18 63 62 REFFREQSEL RCV_PLLRP, RCV_PLLRN RCV_PLLSN, RCV_PLLSP RCV_SYNC RCV_FSEL0, RCV_FSEL1 DOUTOP, DOUT0N, DOUT1P, DOUT1N, DOUT2P, DOUT2N, DOUT3P, DOUT3N CLKOUT2P, CLKOUT2N CLKOUTP, CLKOUTN LFIN RCV_DDRSEL CD Reference Clock Frequency Select (TTL Input): Selects REFCLK frequency of 77.76MHz when LOW or 155.52MHz when HIGH. Clock Recovery PLL Loop Filter: External loop filter pins for the receive PLL. Clock Synthesis PLL Loop Filter: External loop filter pins for the clock synthesis PLL. Receive Synchronizer (TTL Input): Single-ended asynchronous input to set the word boundary on the 4-bit parallel data Receive Frequency Control (TTL Inputs): Two single-ended frequency selects for receive synthesizer. Parallel Data Out (LVDS Outputs): These are the four pairs of receive parallel data outputs. Parallel Clock Out (LVDS Output): This output is the recovered clock at the transmit byte clock rate and provides a clock that can be used as a reference clock to drive CLKIN. Parallel Clock Out (LVDS Output): This output is the recovered clock divided by 4 or 8 to provide the parallel data rate clock. Link Fault Indicator (TTL Output): When HIGH, LFIN indicates CDR is "in-lock" and when LOW it indicates CDR loss-of-lock. Double Data Rate Select (TTL Input): Selects either parallel data rate clock for normal operation or one-half of parallel data rate clock for double data rate applications. Carrier Detect Input (LVPECL input): When HIGH, CD indicates the carrier is present and when LOW it indicates the loss of carrier.
TRANSMIT SECTION SIGNALS 25, 26, 27, 28, 29, 30, 31, 32 22, 23 10, 14 11, 12 49, 50 24 DIN0P, DIN0N, DIN1P, DIN1N, DIN2P, DIN2N, DIN3P, DIN3N CLKINP, CLKINN XMT_FSEL0, XMT_FSEL1 XMT_PLLSN, XMT_PLLSP SOUTP, SOUTN XMT_DDRSEL Parallel Data In (LVDS Inputs): These are the four pairs of transmit parallel data inputs. Each Differential pair has a 100 internal termination across the pair. Parallel Clock In (LVDS Input): This input is the transmit parallel (byte-rate) clock. Transmit Frequency Control (TTL Inputs): Two single-ended frequency selects for transmit synthesizer. Clock Synthesis PLL Loop Filter: External loop filter pins for the clock synthesis PLL. Serial Data Out (Differential CML Output): This is the serial differential data stream output. Double Data Rate Select (TTL Input): Selects either parallel data rate clock for normal operation or one-half of parallel data rate clock for double data rate applications.
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SY87725L
LOOPBACK CONTROLS Pin Number 16, 17 4, 64 Pin Name XMT_CNTRL0, XMT_CNTRL1 RCV_CNTRL0, RCV_CNTRL1 Pin Description Transmit Loop back Multiplexer Control (TTL Inputs): Two single-ended control lines to control the data flow for remote loop back or normal serial data output. Receive Loop back Multiplexer Control (TTL Inputs): Two single-ended control lines to control the data flow for local loop back or recovered serial data into the 1:4 DeMUX.
TRANSLATOR SIGNALS 48 52, 53 IN OUTP, OUTN Signal from MAC to be translated (TTL Input) Signal to Laser Diode Driver (CML Differential Output)
POWER PINS AND TEST PIN 13 20 8 9 19, 38, 47, 54, 57 21, 35, 58 51 Testb Test VCCA GNDA Test Mode Pin: When held LOW activates test mode. (For factory use only, leave open for normal operation.) Test Mode Pin: When held HIGH activates test mode. (For factory use only, must be tied to GND for normal operation.). Analog Power: Connect to +3.3V power supply. Bypass with 0.1F//0.1F low
ESR capacitors as close to VCCA pin as possible.
Analog Ground pin and exposed pad must be connected to the same ground plane.
VCC
GND, Exposed Pad VCCO
Core Power: Connect to +3.3V power supply. Bypass with 0.1F//0.1F low ESR capacitors as close to VCC pins as possible.
Core Ground: Ground pins and exposed pad must be connected to the same ground plane. CML Output Power: Connect to +3.3V power supply. Bypass with
0.1F//0.1F low ESR capacitors as close to VCCO pin as possible.
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SY87725L
Functional Description
The SY87725L is a fully integrated transceiver with an integrated serial-to-4-bit DeMUX and 4-bit-to-serial Multiplexer.
Transmit Section Synthesizer Function
The SY87725L Transmit Synthesizer uses the divide-by4 parallel clock input or a divide-by-8 clock input when double data rate is selected as a reference clock. The XMT_FSEL0 and XMT_FSEL1 inputs select the TX data rate. For example, these inputs can be used to select an OC-24, OC-12 or OC-3 rate for the serial data out, SOUT.
Receive Section Clock and Data Recovery Function
The Clock Recovery function includes a synthesizer that generates a stable frequency based on the REFCLK input. The REFCLK input can be either a differential PECL input or a single-ended TTL input. It can also be either 77.76MHz or 155.52MHz as selected by REFFREQSEL. The synthesized frequency derived from the REFCLK is within 1000ppm of the incoming serial data rate and is used by the Clock and Data Recovery (CDR) circuit to "train" to the correct frequency range. This training function minimizes the acquisition time for the CDR to lock onto the incoming data stream by keeping the CDR frequency within close range of the recovered clock in the case of loss of data. The RCV_FSEL0 and RCV_FSEL1 inputs select the receive data rate. For example, these inputs can be used to select an OC-48, OC-24 or OC-12 data rate for the serial data in, SIN. The typical input sensitivity of SIN is 30mV. The Clock Recovery function also generates CLKOUT2 that is controlled by the XMT_DDRSEL input for regular or double data rate applications. If a clean, low-jitter byte-rate clock is not available for CLKIN to the Transmit Synthesizer, CLKOUT2 can be used as the reference clock.
MUX Function
The 4-bit parallel data input is converted to a serial data stream with a 4:1 multiplexer. The parallel-to-serial conversion sequence is LSB first, i.e. DIN0 will be shifted out first, followed by DIN1, etc.
Auto-Alignment Function
Because the 4-bit parallel data input can have an arbitrary phase relationship with the transmit byte-rate clock input (CLKIN), an auto-alignment function is included in the transmit parallel-to-serial circuit. The phase of the 4-bit parallel data is sampled and compared with the phase of the incoming CLKIN. If the clock and data are not in the proper phase relationship, the phase is internally adjusted to insure that the data will be sampled at the optimal time. This can result in a variation of the latency between the parallel data in and the serial data out (TDOUT) of up to three CLKIN clock cycles.
Loopback Function
Two 3:1 multiplexers are provided to allow Local or Remote Loopback.
DeMUX Function
The recovered serial data from the CDR is converted to a 4-bit parallel word by a 1:4 de-multiplexer. The serialto-parallel conversion sequence is LSB first, i.e. first serial bit in is DOUT0, second serial bit in is DOUT1, etc. A RCV_SYNC pulse input is used to set the word boundary of the 4-bit parallel word. A single pulse, applied asynchronously for a minimum of two input clock cycles to the RCV_SYNC input, causes the start bit of conversion to occur one bit earlier. The CLKOUT output is the parallel data rate clock to be used with the DOUT parallel data from the DeMUX. It is selectable by the RCV_DDRSEL input to be either at the parallel data rate or one-half the parallel data rate for double data rate applications.
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SY87725L
Frequency Selections
XMT_FSEL0 0 1 0 1 XMT_FSEL1 0 0 1 1 TX DATA RATE 155.52Mbps 622.08Mbps 1244.16Mbps N/A
Table 1. Transmit Frequency Selection RCV_FSEL0 0 1 0 1 RCV_FSEL1 0 0 1 1 RX DATA RATE N/A 622.08Mbps 1244.16Mbps 2488.32Mbps
Table 2. Receive Frequency Selection
XMT_FSEL0 0 1 0 1 0 1 0 1
XMT_FSEL1 0 0 1 1 0 0 1 1
XMT_DDRSEL 0 0 0 0 1 1 1 1
CLKOUT2 38.88MHz 155.52MHz 311.04MHz N/A 19.44MHz 77.76MHz 155.52MHz N/A
Table 3. CLKOUT2 Frequency Selection
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SY87725L
RCV_CNTRL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
RCV_CNTRL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
XMT_DDRSEL 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
RCV_DDRSEL 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
DOUT N/A DIN SIN (bypass) SIN (Recovered Data) N/A DIN SIN (bypass) SIN (Recovered Data) N/A DIN SIN (bypass) SIN (Recovered Data) N/A DIN SIN (bypass) SIN (Recovered Data)
CLKOUT N/A CLKIN REFCLK/4 Recovered Clock/4 N/A 2 * CLKIN REFCLK/4 Recovered Clock/4 N/A CLKIN/2 REFCLK/8 Recovered Clock/8 N/A CLKIN REFCLK/8 Recovered Clock/8
Table 4. Local Loopback Controls
XMT_CNTRL0
0 1 0 1
XMT_CNTRL1
0 0 1 1
SOUT
SIN (Bypass CDR) Recovered Clock (from SIN) Recovered Data (from SIN) DIN (Normal Data Flow)
Table 5. Remote Loopback Controls
Loop Filter Components
R Rcv_PLLS Rcv_PLLR XMT_PLLS 1.2k 390 1.2k C 1F 1F 1F
Table 6. Synthesizer & Clock Recovery Loop Filter Values
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SY87725L
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ................................. -0.5V to + 4.6V Input Voltage (VIN)............................................ -0.5V to VCC LVDS Output Current (IOUT)...................................... 10mA CML Outputs Voltage......................................... VCC-1.0V to VCC+0.5V Current ................................................................. 25mA Lead Temperature (soldering, 20 sec.) .................. +260C Storage Temperature (TS) ........................-65C to +150C
Operating Ratings(2)
Supply Voltage (VCC) ............................+3.15V to +3.45V Ambient Temperature (TA) ..................... -40C to +85C (3) Package Thermal Resistance (R) MLF JB Still-Air ............................................................ 35C/W (R) MLF JB Junction-to-Board ............................................ 7C/W
DC Electrical Characteristics(4)
TA = -40C to +85C, unless noted.
Symbol VCC ICC Parameter Power Supply Power Supply Current No load, max. VCC Condition Min 3.15 Typ 3.3 300 Max 3.45 380 Units V mA
LVPECL Electrical Characteristics(4)
VCC = VCCA = VCCO = 3.3V 5%; GND = GNDA = 0V; TA = -40C to +85C, unless otherwise noted.
Symbol VIH VIL Parameter Input HIGH Voltage Input LOW Voltage Condition Min VCC-1.165 VCC-1.810 Typ Max VCC-0.88 VCC-1.475 Units V V
CML Output Electrical Characteristics(4)
VCC = VCCA = VCCO = 3.3V 5%; GND = GNDA = 0V; TA = -40C to +85C, unless otherwise noted.
Symbol VOH VOUT VDIFF_OUT
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package Thermal Resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. JB assumes a 4-layer PCB. JA in still air unless otherwise stated. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter Output HIGH Voltage Output LOW Voltage Differential Output Voltage
Condition
Min VCC-0.020 325 650
Typ VCC-0.010 400 800
Max VCC
Units V mV mV
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SY87725L
LVTTL/CMOS DC Electrical Characteristics(5)
VCC = VCCA = VCCO = 3.3V 5%; GND = GNDA = 0V; TA = -40C to +85C, unless otherwise noted.
Symbol VIH VIL IIH IIL VOH VOL IOS Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Output HIGH Voltage Output LOW Voltage Output Short-Circuit Current IOH = 100A IOl = 4mA VOUT = 0V (max. 1sec.) -100 Condition Min 2.0 0 -125 -300 2.0 0.5 -15 Typ Max VCC 0.8 30 Units V V A A V V mA
LVDS DC Electrical Characteristics(5)
VCC = VCCA = VCCO = 3.3V 5%; GND = GNDA = 0V, RL = 100 across output pair; TA = -40C to +85C, unless otherwise noted.
Symbol Parameter Condition Min Typ Max Units
VIN-Range VIN VDIFF-IN RIN VOUT VDIFF-OUT VOCM VOCM
Note:
Input Voltage Range Input Voltage Swing Differential Input Voltage Swing Input Differential Resistance Output Voltage Swing Differential Output Voltage Swing Output Common Mode Voltage Change in Output Common Mode Voltage
0 100 200 85 100 325 650 1.125 -50
2.4 500 1000 115
V mV mV mV mV
1.275 +50
V mV
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
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SY87725L
AC Electrical Characteristics(6)
VCC = VCCA = VCCO = 3.3V 5%; GND = GNDA = 0V; TA = -40C to +85C, unless otherwise noted
Symbol SINMAX SOUTMAX tACQ Parameter SIN Maximum Data Rate SOUT Maximum Data Rate Acquisition Lock Time Frequency Difference, LFIN shows Out-of-Lock tCPWH tCPWL tSKEW tPR, tPF tLR, tLF tDC
Note: 6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Condition 2.5
Min 1.25
Typ
Max
Units Gbps Gbps
15 1000 2.5 2.5 See "Figure 1" At full output swing At full output swing -150 40 100 45 70 250 +150 100 400 55
s ppm ns ns ps ps ps %
REFCLK Pulse Width HIGH Time REFCLK Pulse Width LOW Time Parallel CLKOUT to Parallel Data Out Skew CML Output Rise/Fall Time (20% to 80%) LVDS Output Rise/Fall Time (20% to 80%) CLKOUT, CLKOUT2 Duty Cycle
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SY87725L
Timing Diagrams
Receive Timing
INTERNAL CLK SIN DOUT0 DOUT1 DOUT2 DOUT3 CLKOUT(Normal Mode) CLKOUT(Half Rate Mode)
tSKEW D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
Figure 1. 1:4 Serial-to-Parallel Conversion
INTERNAL CLK SIN SYNC DOUT0 DOUT1 DOUT2 DOUT3 CLKOUT(Normal Mode) CLKOUT(Half Rate Mode)
D0 D1 D2 D3 D5 D6 D7 D8 D0 D1 D2 D3 D4 D5 D6 D7 D8
Figure 2. 1:4 Serial-to-Parallel Conversion with SYNC Pulse
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SY87725L
Transmit Timing
CLKIN (Normal Mode) CLKIN (Half Rate Mode) DIN0 DIN1 DIN2 DIN3 INTERNAL SERIAL CLK SOUT
D0 D1 D2 D3 D0 D1 D2 D3 D4 D5 D6 D7
Figure 3. 4:1 Parallel-to-Serial Conversion
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SY87725L
Applications Sections
This section illustrates the various operating modes of the SY87725L with the appropriate control signals. Transmit Section On the transmit side, the upstream data appears at DIN in a 4-bit wide parallel format at 312.5Mbps and exits at SOUT at a 1.25Gbps serial rate. The CLKIN input is synchronous with the parallel data at DIN. The loopback control signals RCV_CNTRL0, RCV_CNTRL1, XMT_CNTRL0, XMT_CNTRL1 shown in the table below select the clock and data paths for normal operation. The RCV_DDRSel input is selecting the CLKOUT to be in normal rate (/ 4) mode.
Normal Data Flow
Receive Section The diagram below shows the data paths in a normal operating mode. In this case, downstream data at a serial rate of 2.5Gbps is arriving at SIN and the recovered 4-bit parallel data is exiting at DOUT at 625Mbps. This is not the double data rate mode (DDR) so the parallel rate is the serial rate / 4.
Figure 4. Normal Data Flow RCV_CNTRL0 1 RCV_CNTRL1 1 XMT_CNTRL0 1 XMT_CNTRL1 1 RCV_DDRSEL 0
Table 7. Loopback and DDR Select Control Signals RCV_FSEL0 1 RCV_FSEL1 1 XMT_FSEL0 0 XMT_FSEL1 1
Table 8. Transmit and Receive Frequency Select
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SY87725L previous section, but utilizes CLKOUT2 to be used as the transmit parallel clock. In this mode, CLKOUT2 must be externally connected to CLKIN as shown in the block diagram below.
Normal Data Flow (Secondary Clock)
Receive Section This mode is identical to the Normal Mode in the
Figure 5. Normal Data Flow RCV_CNTRL0 1 RCV_CNTRL1 1 XMT_CNTRL0 1 XMT_CNTRL1 1 RCV_DDRSEL 0
Table 9. Loopback and DDR Select Control Signals RCV_FSEL0 1 RCV_FSEL1 1 XMT_FSEL0 0 XMT_FSEL1 1
Table 10. Transmit and Receive Frequency Select
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SY87725L It is possible to combine this with Local Loopback modes; however, it is intended to be a stand-alone test mode.
Remote Loopback Mode 00
This is the simplest of the loopback modes as its main purpose is to verify if the link is OK.
Figure 6. Remote Loopback Data Flow XMT_CNTRL0 0 XMT_CNTRL1 0
Table 11. Loopback Control Signals
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SY87725L looping back the recovered clock or data. The REFCLK is necessary for normal operation of the CDR.
Remote Loopback Modes 01 and 10
These modes verify the operation of the CDR by
Figure 7. Remote Loopback Recovered Clock Flow XMT_CNTRL0 1 XMT_CNTRL1 0
Table 12. Loopback Control Signals
Figure 8. Remote Loopback Recovered Data Flow XMT_CNTRL0 0 XMT_CNTRL1 1
Table 13. Loopback Control Signals
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SY87725L Therefore, in this mode only, the RefClk is not used by the Synthesizer but will be at the same frequency as the SIN data rate. In this mode the maximum SIN data rate is 155.52Mbps and the matching RefClk frequency will be 155.52MHz. The Data at SIN is sampled at the falling edge of REFCLK.
CDR Bypass Mode
This mode bypasses the CDR and feeds SIN directly into the DeMUX. Because the CDR is bypassed, there is no recovered clock in this mode. The RefClk is fed directly into the DeMUX and is the serial rate clock.
Figure 9. CDR Bypass Mode RCV_CNTRL0 0 RCV_CNTRL1 1
Table 14. Loopback Control Signals
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SY87725L operation of the Mux and DeMux to be verified through the parallel interface.
Local Loopback Mode
This mode loops the serial data out of the Mux back to the serial input of the DeMux. This allows the
Figure 10. Local Loopback Data Flow RCV_CNTRL0 1 RCV_CNTRL1 0
Table 15. Loopback Control Signals
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SY87725L
Package Information
64-Pin EPAD-TQFP (T64-1)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated.
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